Design of X-ray data transmission system for ray industry (Part 2)

2 Software designFig. 2 Connection between EZUSBFX2andFPGA Figure 2 EZUSBF The connection transmission system software between X2 and FPGA includes FPGA control program, firmware program, driver and PC application program. 2.1 FPGA programming The FPGA subsystem principle block diagram is shown in Figure 1. The FPGA mainly completes receiving serial data and sending data to the EZ-USBFX2 module. The FPGA subsystem receives and caches the multi-channel serial data sent by the detector, and then waits until the data is cached to a certain extent, then transmits it to the EZ-USBFX2 chip, and then the USB chip will automatically transmit the data to the host computer through USB.

FPGA contains two channels internally: data channel and command channel. What flows through the data channel is projection data (data obtained by each channel each time the detector is illuminated). As shown in Figure 1, the projection data of each channel is first stored in the corresponding cache FIFO, and waits until the data in the FIFO After the data reaches a certain amount (here it is set to 512), the FPGA will transfer a certain amount of data (here 512) from each FIFO to the endpoint buffer of EZ-USB FX2.

The command channel is mainly used for the transmission of configuration commands. When the host computer issues a configuration command, the USB transmits the command to the FPGA through SlaveFIFO. Then the FPGA stores the received command data in the configuration RAM. Finally, the FPGA internal The command configuration module passes Query the changes in the value in the configuration RAM to determine whether a command should be sent to the detector.

The FPGA program contains a total of 7 modules, as shown in Figure 3. Among them, the synchronization FIFO and configuration RAM use ALTERA’s IP; the serial receiving module and the serial sending module mainly complete the sending and receiving of serial data; the configuration CPU module monitors the status of the configuration RAM. If the value of the configuration RAM changes, the configuration CPU module monitors the status of the configuration RAM. The serial sending module sends the changed value to the detector; the configuration RAM stores the configuration command synchronization FIFO and stores the projection data bus. The arbitration module controls the FIFO data bus and the configuration RAM bus, which ensures the timeliness of the command configuration and the integrity of the data transmission; SlaveFIFO The interface module realizes the communication between FPGA and EZ-USBFX2.

DTU/Edge Gateway/IoT Platform/Gateway Module

2.2 Firmware program 2.2.1 The role of firmware Firmware refers to the executable code running in the enhanced 8051EEPROM in EZ-USBFX2 (CY7C68013A). Firmware can be developed using assembly language or C51, and then compiled into a hexadecimal file (.HEX file) and written to the code area in FX2, thereby realizing device-side programming and completing specific functions. The firmware program mainly completes the following work: ① Initialization work, including setting the initial values ​​of some special function registers to achieve the required device attributes or functions;

② Assist the hardware to complete the re-enumeration process of the device, including simulating the disconnection and reconnection of the device, analyzing and judging the received setting packet, so as to make an appropriate response to the host’s device request and complete the host’s configuration task of the device; ③Handling of interrupts; ④Receiving and sending data; ⑤Control of peripheral circuits. 2.2.2 Communication between USB device and PC USB device communicates with PC-side application program under the control of microcontroller to realize USB data sending and receiving. The basic process is: when the USB peripheral is connected to the host, the host First enumerate the device, then download the firmware program to its on-chip RAM through the default endpoint EP0, then re-enumerate the device, and configure the device with the firmware downloaded to its internal RAM, that is, the mode designed by the user, according to the user-defined firmware program VID and PID to find the function driver of the device, thereby completing the device configuration process. During the process of transmitting data, the sent data is written into the buffer (FIFOBuffer) in the form of a packet (Pack et). When the buffer is filled or the data is sent, USB sets the register full flag. If the host is ready to accept data, it sends a read token packet to the functional device endpoint. The endpoint responds to the request by judging the endpoint type and whether it is ready to send data. After completing the data transmission, the entire communication process is completed through a handshake packet. 2.2.3 Slave FIFO mode firmware program development FX2 provides two interface modes: slave FIFO and general programmable interface. The data transmission system adopts slave FIFO mode, and its firmware mainly includes 7 files: dscr. a51,lsecyJmpTb. a51, lsecy. h, lsecysdly. h, lsecyregs. h, main. c and function. c. The firmware is stored on the PC. When the device is connected to the host, the firmware is loaded from the host to the EZ-USBFX2 on-chip RAM through soft configuration for execution.

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